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Catapult LP for a Power Optimized ESL Hardware Realization Flow

ABSTRACT   High-level synthesis (HLS) allows designers to synthesize different RTL architectures from C++ or SystemC electronic system level (ESL) models. The different hardware architectures are...

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Implementing an Efficient RTL Clock Gating Analysis Flow at AMD

Lowering the power consumption of consumer products and networking centers is an important design consideration. The same goes for many of the chips that go into these devices. AMD is building a...

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RTL Clock Gating Analysis Cuts Power by 20% in AMD Chip

Lowering the power consumption of consumer products and networking centers is an important design consideration, and this effort begins with many of the chips that go into these devices....

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Low Power RTL Report 2012

This report covers trends in the area of low power design, based on an independent, global RTL power analysis and optimization survey.   The survey was executed in late 2011 and had 744 SoC, IC, and...

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RTL Power Reduction and High Level Synthesis Report 2013

Download Report       This year’s annual report has two sections based on an independent worldwide survey: 1) RTL power reduction; 2) High Level Synthesis.   648 SoC, IC, and FPGA design professionals...

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AMD’s Methodology Reduces Power by 20%

This paper provides an overview of how AMD used PowerPro to improve clock-gating efficiency, and shares the results and advantages of doing power analysis at the RTL stage rather than waiting until...

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Implementing an Efficient RTL Clock Gating Analysis Flow at AMD

This paper provides an overview of how AMD used PowerPro to improve clock-gating efficiency, and shares the results and advantages of doing power analysis at the RTL stage rather than waiting until...

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